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| ITF86172SK8T Data Sheet January 2000 File Number 4809.1 10A, 30V, 0.016 Ohm, P-Channel, Logic Level, Power MOSFET Features * Ultra Low On-Resistance [ /Title - rDS(ON) = 0.016, VGS = -10V Packaging (HUF7 - rDS(ON) = 0.023, VGS = -4.5V SO8 (JEDEC MS-012AA) - rDS(ON) = 0.026, VGS = -4V 6400S BRANDING DASH * Gate to Source Protection Diode K8) * Simulation Models /Sub- Temperature Compensated PSPICETM and SABER ject 5 Electrical Models (60V, - Spice and SABER Thermal Impedance Models 1 0.072 2 - www.intersil.com 3 Ohm, 4 * Peak Current vs Pulse Width Curve 4A, N* Transient Thermal Impedance Curve vs Board Mounting ChanSymbol Area nel, * Switching Time vs RGS Curves Logic SOURCE(1) DRAIN(8) Level Ordering Information SOURCE(2) DRAIN(7) UltraFE T PART NUMBER PACKAGE BRAND Power ITF86172SK8T SO8 86172 SOURCE(3) DRAIN(6) MOSNOTE: When ordering, use the entire part number. ITF86172SK8T DRAIN(5) is available only in tape and reel. GATE(4) FET) /Author () /Keywords Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified ITF86172SK8T UNITS (InterDrain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS -30 V sil Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR -30 V SemiGate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS 20 V conduc- Drain Current tor, NContinuous (TA= 25oC, VGS = 10V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 10.0 A Continuous (TA= 25oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 8.0 A ChanContinuous (TA= 100oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 5.0 A nel, Continuous (TA= 100oC, VGS = 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 5.0 A Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Figure 4 Logic Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 2.5 W Level Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mW/oC UltraFE Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T oC -55 to 150 J STG T Maximum Temperature for Soldering oC Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL 300 Power o Package Body for 10s, See Tech brief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. TJ = 25oC to 125oC. 2. 50oC/W measured using FR-4 board with 0.76 in2 (490.3 mm2) copper pad at 10 second. 1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. SABER(c) is a Copyright of Analogy Inc.http://www.intersil.com or 321-727-9207 | Copyright (c) Intersil Corporation 1999 ITF86172SK8T Electrical Specifications PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS(TH) rDS(ON) VGS = VDS, ID = 250A Figure 10 ID = 10.0A, VGS = -10V Figures 8,9 ID = 5.0A, VGS = -4.5V Figure 8 ID = 5.0A, VGS = -4.0V Figure 8 THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.76 in2 (490.3 mm2) (Note 2) Pad Area = 0.054 in2 (34.8 mm2) Figure 20 Pad Area = 0.0115 in2 (7.42 mm2) Figure 20 SWITCHING SPECIFICATIONS (VGS = -4.5V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time SWITCHING SPECIFICATIONS (VGS = -10V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at -5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = -25V, VGS = 0V, f = 1MHz Figure 12 1930 470 215 pF pF pF Qg(TOT) Qg(-5) Qg(TH) Qgs Qgd VGS = 0V to -10V VGS = 0V to -5V VGS = 0V to -1V VDD = -15V, ID = 8.0A, Ig(REF) = -1.0mA Figures 13, 16, 17 38 22 2 6.8 9.2 nC nC nC nC nC td(ON) tr td(OFF) tf VDD = -15V, ID = 10.0A VGS = -10V, RGS = 7.5 Figures 15, 18, 19 12 81 76 80 ns ns ns ns td(ON) tr td(OFF) tf VDD = -15V, ID = 5.0A VGS = -4.5V, RGS = 7.5 Figures 14, 18, 19 20 87 48 62 ns ns ns ns 50 152 189 oC/W oC/W oC/W TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS BVDSS IDSS IGSS ID = 250A, VGS = 0V Figure 11 VDS = -30V, VGS = 0V VGS = 20V -30 - - -1 10 -2.5 0.016 0.023 0.026 V A uA -1.0 - 0.0125 0.017 0.019 V Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = -8.0A ISD = -8.0A, dISD/dt = 100A/s ISD = -8.0A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP -0.8 26 13 MAX UNITS V ns nC 2 ITF86172SK8T Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) -12 -10 -8 -6 -4 -2 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) VGS = -4.0V, RJA = 189oC/W VGS = -10V, RJA = 50oC/W FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE 3 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM ID, DRAIN CURRENT (A) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE THERMAL IMPEDANCE RJA = 50oC/W ZJA, NORMALIZED 0.1 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 101 102 103 SINGLE PULSE 0.001 10-5 10-4 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE -800 RJA = 50oC/W IDM, PEAK CURRENT (A) TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125 -100 VGS = -4.5V -10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103 -5 10-5 FIGURE 4. PEAK CURRENT CAPABILITY 3 ITF86172SK8T Typical Performance Curves -500 RJA = 50oC/W (Continued) -40 SINGLE PULSE TJ = MAX RATED TA = 25oC ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V -100 100s ID, DRAIN CURRENT (A) -30 -20 TJ = 150oC -10 TJ = 25oC TJ = -55oC -1.5 -2.0 -2.5 -3.0 VGS, GATE TO SOURCE VOLTAGE (V) -3.5 -10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 10ms -1 -1 -10 VDS, DRAIN TO SOURCE VOLTAGE (V) -60 0 FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. TRANSFER CHARACTERISTICS -40 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 30 VGS = -10V VGS = -5V VGS = -4.5V VGS = -4V VGS = -3.5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = -10A ID, DRAIN CURRENT (A) -30 25 VGS = -3V -20 20 ID = -2A -10 TA = 25oC 0 0 -0.5 -1.0 VDS, DRAIN TO SOURCE VOLTAGE (V) -1.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 15 10 -2 -3 -5 -7 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) -9 -10 FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.4 VGS = -10V, ID = -10A NORMALIZED GATE THRESHOLD VOLTAGE 1.2 VGS = VDS, ID = -250A 1.0 1.2 1.0 0.8 0.8 0.6 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 0.6 0.5 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 4 ITF86172SK8T Typical Performance Curves 1.10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE (Continued) 3000 ID = -250A COSS CDS + CGD 1000 CISS = CGS + CGD 1.05 1.00 0.95 C, CAPACITANCE (pF) CRSS = CGD 0.90 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) VGS = 0V, f = 1MHz 100 -0.1 -1.0 -10 -30 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = -15V -8 FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 250 VGS = -4.5V, VDD = -15V, ID = -5A SWITCHING TIME (ns) 200 tr tf 150 td(OFF) -6 -4 WAVEFORMS IN DESCENDING ORDER: ID = -10A ID = -2A 0 10 20 30 Qg, GATE CHARGE (nC) 40 100 -2 50 td(ON) 0 0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50 NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 14. SWITCHING TIME vs GATE RESISTANCE 300 VGS = -10V, VDD = -15V, ID = -10A 250 SWITCHING TIME (ns) 200 tf 150 100 50 0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50 tr td(OFF) td(ON) FIGURE 15. SWITCHING TIME vs GATE RESISTANCE 5 ITF86172SK8T Test Circuits and Waveforms Qgs RL 0 VGS= -1V VGS VDD + VDS Qgd VDS Qg(TH) -VGS Qg(-5) VDD Qg(TOT) 0 Ig(REF) VGS= -5V DUT Ig(REF) VGS= -10V FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS tON td(ON) RL VDS VGS + tOFF td(OFF) tr tf 10% 10% 0 0V RGS -VGS DUT 0 VDS 90% 90% 10% 50% VGS PULSE WIDTH 90% 50% FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. ( T JM - T A ) P DM = -----------------------------Z JA 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the (EQ. 1) In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 6 ITF86172SK8T necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 23 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. R JA = 83.2 - 23.6 x Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 240 RJA = 83.2 - 23.6*ln(AREA) 200 RJA (oC/W) 189oC/W - 0.0115in2 160 152oC/W - 0.054in2 ln ( Area ) (EQ. 2) 120 The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. 150 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2 80 0.01 0.1 AREA, TOP COPPER AREA (in2) 1.0 FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA 120 ZJA, THERMAL IMPEDANCE (oC/W) 90 60 30 0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA 7 ITF86172SK8T PSPICE Electrical Model .SUBCKT ITF86172SK8 2 1 3 ; CA 12 8 1.70e-9 CB 15 14 1.70e-9 CIN 6 8 1.80e-9 DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -35.25 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 1.29e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.90E-3 RGATE 9 20 5.20 RLDRAIN 2 5 10 RLGATE 1 9 9 10.4 RLSOURCE 3 7 1.29 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 7.75e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD LGATE GATE 1 RLGATE DESD1 91 DESD2 CIN RGATE 9 EVTEMP ESG 10 LDRAIN + 5 RLDRAIN EBREAK ESLC 50 DBODY + 17 18 DRAIN 2 RSLC1 51 REV 24 November 1999 - 8 6 RSLC2 5 51 DPLCAP EVTHRES + 19 8 6 - 20 18 + 22 S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17 - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),9))} .MODEL DBODYMOD D (IS = 3.00e-12 RS = 7.15e-3 TRS1 = 1.54e-3 TRS2 = -2.48e-6 CJO = 1.25e-9 TT = 6.5e-10 VJ=0.65 M = 0.44) .MODEL DBREAKMOD D (RS = 1.50e-1 TRS1 = 1.00e-3 TRS2 = 1.00e-6) .MODEL DESD1MOD D (BV=18.3 TBV1=-1.43E-3 TBV2=0 RS=100 N=13) .MODEL DESD2MOD D (BV=18.15 TBV1=-1.43E-3 TBV2=0 RS=100 N=13) .MODEL DPLCAPMOD D (CJO = 9.20e-10 IS = 1e-30 N=10 VJ=0.4 M = 0.36) .MODEL MMEDMOD PMOS (VTO = -1.61 KP = 2.6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.20) .MODEL MSTROMOD PMOS (VTO = -1.94 KP = 55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u LAMBDA=0.014) .MODEL MWEAKMOD PMOS (VTO = -1.35 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 52.0) .MODEL RBREAKMOD RES (TC1 = 6.70e-4 TC2 = -1.02E-6) .MODEL RDRAINMOD RES (TC1 = 1.24e-2 TC2 = 7.00e-6) .MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = -3.00e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = 1.50e-3 TC2 = 6.20e-6) .MODEL RVTEMPMOD RES (TC1 = -1.00e-3 TC2 = 0) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = 6.2 VOFF= 3.1) VON = 3.1 VOFF= 6.2) VON = 1.0 VOFF= -0.5) VON = -0.5 VOFF= 1.0) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 8 + - - RDRAIN 21 16 MWEAK MMED MSTRO 8 RSOURCE DBREAK 11 LSOURCE 7 RLSOURCE SOURCE 3 RBREAK 18 RVTEMP 19 VBAT + 8 22 RVTHRES ITF86172SK8T SABER Electrical Model REV 24 November1999 template ITF86172SK8 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 3.00e-12, cjo = 1.25e-9, tt = 6.5e-10, vj=0.65, m = 0.44, rs = 7.15e-3, trs1 = 1.54e-3, trs2 = -2.48e-6) dp..model dbreakmod = (rs = 1.5e-1, trs1 = 1.00e-3, trs2 = 1.00e-6) dp..desd1mod = (bv=18.3, tbv1=-1.43e-3, tbv2=0, rs=100, nl=13) dp..desd2mod = (bv=18.15, tbv1=-1.43e-3, tbv2=0, rs=100, nl=13) dp..model dplcapmod = (cjo = 9.20e-10, isl = 1e-30, nl = 10, vj=0.4, m = 0.36) m..model mmedmod = (type=_p, vto = -1.61, kp = 2.6, is = 1e-30, tox = 1) m..model mstrongmod = (type=_p, vto = -1.94, kp = 55, is = 1e-30, tox = 1, lambda=0.014) ESG m..model mweakmod = (type=_p, vto = -1.35, kp = 0.08, is = 1e-30, tox = 1) 5 sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 6.2, voff = 3.1) -8+ 6 sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 3.1, voff = 6.2) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 1.0, voff = -0.5) + 10 RSLC1 sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 1.0) EBREAK 17 51 LDRAIN DRAIN 2 RLDRAIN c.ca n12 n8 = 1.70e-9 c.cb n15 n14 = 1.70e-9 c.cin n6 n8 = 1.80e-9 dp.dbody n5 n7 = model=dbodymod dp.dbreak n7 n11 = model=dbreakmod dp.dplcap n10 n6 = model=dplcapmod dp.desd1 n91 n9 = model=desd1mod dp.desd2 n91 n7 = model=desd2mod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.04e-9 l.lsource n3 n7 = 1.29e-10 DPLCAP RSLC2 ISCL 50 RDRAIN EVTHRES + 19 8 6 MSTRO CIN 16 21 MMED 11 18 LGATE GATE 1 RLGATE 91 RGATE 9 EVTEMP MWEAK - DBODY 20 DESD1 DESD2 18 + 22 DBREAK 8 RSOURCE 7 LSOURCE SOURCE 3 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 6.70e-4, tc2 = -1.02e-6 res.rdrain n50 n16 = 2.90e-3, tc1 = 1.24e-2, tc2 = 7.00e-6 res.rgate n9 n20 = 5.20 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10.4 res.rlsource n3 n7 = 1.29 res.rslc1 n5 n51 = 1e-6, tc1 = 2.00e-3, tc2 = -3.00e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 7.75e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.00e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = 1.50e-3, tc2 = 6.20e-6 spe.ebreak n11 n7 n17 n18 = -35.25 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n5 n10 n8 n6 = 1 spe.evtemp n6 n20 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 12 CA RLSOURCE S1A S2A RBREAK 13 8 S1B 13 + EGS 6 8 EDS 14 13 S2B CB + 5 8 14 IT 15 17 18 RVTEMP 19 VBAT + - - 8 RVTHRES 22 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 9)) } } 9 ITF86172SK8T SPICE Thermal Model REV 28 July 1999 ITF86172SK8 Copper Area = 0.76 in2 CTHERM1 th 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2.0e-1 CTHERM7 3 2 1 CTHERM8 2 tl 3 RTHERM1 th 8 0.1 RTHERM2 8 7 0.5 RTHERM3 7 6 1.0 RTHERM4 6 5 5.0 RTHERM5 5 4 8.0 RTHERM6 4 3 13 RTHERM7 3 2 19 RTHERM8 2 tl 29.7 th JUNCTION RTHERM1 8 CTHERM1 RTHERM2 7 CTHERM2 RTHERM3 6 CTHERM3 SABER Thermal Model Copper Area = 0.76 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 2.0e-3 ctherm.ctherm2 8 7 = 5.0e-3 ctherm.ctherm3 7 6 = 1.0e-2 ctherm.ctherm4 6 5 = 4.0e-2 ctherm.ctherm5 5 4 = 9.0e-2 ctherm.ctherm6 4 3 = 2.0e-1 ctherm.ctherm7 3 2 = 1 ctherm.ctherm8 2 tl = 3 rtherm.rtherm1 th 8 = 0.1 rtherm.rtherm2 8 7 = 0.5 rtherm.rtherm3 7 6 = 1.0 rtherm.rtherm4 6 5 = 5.0 rtherm.rtherm5 5 4 = 8.0 rtherm.rtherm6 4 3 = 13 rtherm.rtherm7 3 2 = 19 rtherm.rtherm8 2 tl = 29.7 } RTHERM4 5 CTHERM4 RTHERM5 4 CTHERM5 RTHERM6 3 CTHERM6 RTHERM7 2 CTHERM7 RTHERM8 CTHERM8 tl CASE TABLE 1. Thermal Models COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.04 in2 1.2e-1 0.5 1.3 26 39 55 0.28 in2 1.5e-1 1.0 2.8 20 24 38.7 0.52 in2 2.0e-1 1.0 3.0 15 21 31.3 0.76 in2 2.0e-1 1.0 3.0 13 19 29.7 1.0 in2 2.0e-1 1.0 3.0 12 18 25 10 MS-012AA E E1 1 e 2 A ITF86172SK8T 8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE INCHES A1 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00 NOTES 2 3 4 SYMBOL A A1 b c MIN 0.0532 0.004 0.013 0.0075 0.189 0.2284 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.244 0.1574 D 6 D b E E1 e H 5 h x 45o 0.050 BSC 0.0099 0.016 0.0196 0.050 1.27 BSC 0.25 0.40 0.50 1.27 c L L 0.060 1.52 0o-8o 0.004 IN 0.10 mm 0.050 1.27 0.024 0.6 0.155 4.0 0.275 7.0 MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE-MOUNTED APPLICATIONS NOTES: 1. All dimensions are within allowable dimensions of Rev. C of JEDEC MS-012AA outline dated 5-90. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.010 inches (0.25mm) per side. 4. "L" is the length of terminal for soldering. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. Controlling dimension: Millimeter. 7. Revision 8 dated 5-99. 1.5mm DIA. HOLE 4.0mm USER DIRECTION OF FEED 2.0mm 1.75mm C L MS-012AA 12mm TAPE AND REEL 12mm 8.0mm 40mm MIN. ACCESS HOLE 18.4mm COVER TAPE 13mm 330mm 50mm GENERAL INFORMATION 1. 2500 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS. 12.4mm 11 ITF86172SK8T All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 12 |
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